SystemVerilog for Hardware Description: RTL Design and Verification

Logic Design and Verification Using SystemVerilog (Revised)

RTL Modeling with SystemVerilog for Simulation and Synthesis: Using ASIC FPGA Design

Crack the Hardware Interview from RTL Designers' Perspective: Verification, Implementation, Synthesis & Power

Finite State Machines in Hardware: Theory and Design (with VHDL SystemVerilog)