Verification Techniques for System-Level Design (Systems on Silicon)

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Amazon Pages: 256, Edition: 1, Hardcover, Morgan Kaufmann
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Pages: 256, Edition: 1, Hardcover, Morgan Kaufmann

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Brand Morgan Kaufmann
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  • 9780123706164

Morgan Kaufmann

Verification Techniques for System-Level Design (ISSN)

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Morgan Kaufmann

Electronic Design Automation: Synthesis, Verification, and Test (Systems on Silicon)

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Electronic Design Automation: Synthesis, Verification, and Test (Systems on Silicon)

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System-Level Design Techniques for Energy-Efficient Embedded Systems

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