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VLSI Logic SYNTHESIS: RTL-to-Gate-Level Design, Optimization, Technology Mapping, Timing Constraints, and Power-Aware Synthesis (VLSI Design & Semiconductor Engineering)

Name: VLSI Logic SYNTHESIS: RTL-to-Gate-Level Design, Optimization, Technology Mapping, Timing Constraints, and Power-Aware Synthesis (VLSI Design & Semiconductor Engineering)
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SKU: 2984567e43226ecf38467d4aa4d1a8c4

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VLSI Logic SYNTHESIS: RTL-to-Gate-Level Design, Optimization, Technology Mapping, Timing Constraints, and Power-Aware Synthesis (VLSI Design & Semiconductor Engineering)